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Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.

Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.

At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.

Xilinx has reworked its Versal FPGA for edge-AI applications.