DAC 2014 offers free exhibit entry for three days
The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
EDA
Mentor’s User2User Silicon Valley conference this week
Registration is free-of-charge to attend Mentor, Oracle and Samsung keynotes and choose from nine technical tracks at one-day event.
Intel and Altera extend foundry deal into interposer and full 3D
Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
Even EUV faces a 1D future, says IMEC
IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Synopsys begins IC Compiler II roll-out
New data model and optimisation strategy, plus revised analysis engines update Synopsys's IC Compiler place and route tool
Mentor buys BDA for AMS portfolio
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
ADC design shifts gears for lower power
SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Cadence uses SQL to boost verification manager capacity
Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
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