Mentor buys BDA for AMS portfolio
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
EDA
ADC design shifts gears for lower power
SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Cadence uses SQL to boost verification manager capacity
Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
MIPS brings virtualization and tamper protection to 32bit MCUs
Imagination Technologies' MIPS group has launched processor cores that include support for virtualization and measures to prevent reverse engineering.
DVCon sets up in Europe
Verification conference DVCon is expanding into Europe with a two-day conference and show at the Hilton in Munich, Germany.
Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%
Uses improved logic optimisations and a new approach to meeting timing.
Capacity may force uptick in chip prices, says analyst
Chip pricing could see a significant uptick because of reduced investment in fab capacity, according to Future Horizons.
Cadence updates Incisive with formal, CRV, wreal additions
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Inside Secure to offer IP for mobile hardware vaults
Inside Secure has developed a set of certification-ready hardware IP modules that can be used stand-alone or in conjunction with ARM's TrustZone