On-chip interconnect startup uses network theory to sidestep deadlocks
NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
EDA
Pulsic opts for “layout early, layout often” strategy
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Vorsprung durch 3D technik for Audi
The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
Multicore fastSpice extends reach
Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.
Cadence signs with ARM for core optimizations
Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Cadence ports IP and qualifies tools for 28nm FD-SOI
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Samsung agrees to make 28nm FD-SOI
STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
Mentor targets 10X cut in reliability test for power electronics
New MicReD power tester identifies failure causes without the need for post-test lab analysis
Cadence to expand formal portfolio with Jasper buy
Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
FinFET variability issues challenge advantages of new process
Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.