January 14, 2021
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
February 26, 2019
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
May 24, 2014
More lint rules, better SystemVerilog support, links to MATLAB and Simulink