static analysis


January 14, 2021

A new methodology addresses the increasing challenge of reset domain crossing

Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Article  |  Topics: Case Study, Verification  |  Tags: ,   |  Organizations: ,
February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Article  |  Topics: Blog Topics, HLS, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
Article  |  Topics: Product, Verification  |  Tags: , , , , ,   |  Organizations:

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