Verilog-AMS

March 4, 2024

Latest version of Verilog-AMS ready for release

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.

Article | Topics: Blog - EDA | Tags: standards, SystemVerilog, Verilog-AMS | Organizations: Accellera

June 7, 2015

Speedy software creation to show off custom-tool possibilities

Invionics will be using its software environment to create a custom tool within just two days at the 52nd DAC.

Article | Topics: Blog - EDA | Tags: custom tools, DAC 2015, netlist, Verilog-AMS | Organizations: Concept Engineering, Invionics

June 10, 2014

Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.

Article | Topics: Blog - EDA | Tags: DAC 2014, mixed-signal design, real-value modelling, SystemVerilog, verification, Verilog-AMS | Organizations: Accellera

May 8, 2013

CDNLive EMEA: Embedded processors could surge past mobile at ARM in a few years

ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.

Article | Topics: Blog - EDA, Embedded | Tags: CDNLive EMEA 2013, Cortex M0, MCU, mixed-signal design, Verilog-AMS, white-space radio | Organizations: Arm, Cadence Design Systems

Related Technical Articles

Characterizing PLL jitter from power supply fluctuations using mixed-signal simulations

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL jitter mechanisms, jitter from CMOS gate switching threshold variation due to power supply fluctuations has been chosen as the focus. Analog-to-digital converters carrying dynamic power supply dependency are used together with behavioral models written in Verilog-AMS to approximately model and characterize the targeted type of jitter.

PLATINUM SPONSORS

View All Sponsors