Accellera Systems Initiative has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
The aim of the mixed-signal interface working group is to propose SystemVerilog-compatible language extensions to permit interconnect, conversion, and resolution of dissimilar net types in the verification language.
Accellera chair Lu Dai said, “The SystemVerilog MSI standard will create efficiencies for engineers using the upcoming Verilog-AMS and UVM-MS standards by making it easier to connect analog and mixed-signal models to SystemVerilog designs.”
The new working group will be chaired by Tom Fitzpatrick, who is also chair of the UVM-MS, formerly UVM-AMS, and IEEE Std 1800 working groups, and co-chaired by Peter Grove, who is also the SystemVerilog-AMS working-group chair and UVM-MS co-chair. The aim is to release the extensions in an addendum to IEEE 1800-2023.
“We expect this new functionality to enable the SystemVerilog-AMS standard to bypass some limitations that were present in Verilog-AMS,” added Grove.
The extensions will include support for bidirectional net connections between logic or user-defined nets and analog or physical signals and aim to overcome issues with prior attempts made outside IEEE 1800.
The first meeting of the working group is planned for mid-March.