Latest version of Verilog-AMS ready for release

By Chris Edwards |  No Comments  |  Posted: March 4, 2024
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.

Accellera chair Lu Dai said, “The Verilog-AMS 2023 update significantly bolsters analog-specific functionalities while also facilitating compatibility with the UVM-MS standard, further aligning the standards.”

The Verilog-AMS standard supports analog and mixed-signal designs expressed using mixtures of up to three levels: transistor; gate; and behavioral. Updates to the Verilog-AMS 2023 standard include jump statements for analog constructs, clarifications to some of the language features, such as interrupted transitions and named events, and compiler directives for use with UVM-MS.

“As an avid Verilog-AMS power user myself, I had firsthand feedback on areas within the standard that warranted improvement,” said Peter Grove, chair of the SystemVerilog-AMS working group. “Our working group members evaluated all feedback and worked together to improve the language. This team effort of EDA companies and users alike demonstrates the continued commitment towards advancing the standard.”

The updated standard is available to download fee-free. The organization has also arranged with the IEEE to make the latest version of the SystemVerilog standard available for free as part of the GET Program.

“Our close partnership with the IEEE Standards Association provides engineers with much needed standards fee-free,” Dai said. “As a sponsor of the IEEE GET Program for over 13 years, engineers worldwide have access to the standards they need to help improve design and verification of advanced integrated circuits and embedded systems.”

“The 2023 revision builds on the long history of SystemVerilog and the expertise of the many volunteers who have worked on the various versions of the standard for more than 20 years,” said Tom Fitzpatrick, IEEE 1800 working-group chair. “This version includes several enhancements to extend the capabilities of the language or to formalize features previously implemented as ad hoc additions in some tools. It also fixes several errata ranging from typographical errors to inconsistencies in previous versions and clarifies areas where previous versions were ambiguous.”

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