At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells, which has becoming more troublesome as track heights continue to reduce in the quest for improved PPA at denser process nodes.
Yongchan Ban, senior member of technical staff at GlobalFoundries, said the conventional 1:1 ratio between the pitch of densest metal layer (M1) and that of the gate poses problems for routing because, with only four or five tracks to play with, each input to a cell may have only one contact pin. “The object of this work is to improve pin accessibility by pushing M1 pitches,” Ban said.
The foundry’s engineers tried moving the gearing to three metal lines for every two gates to see how this would affect the number of pin connections. The shift to a 3:2 gearing introduces a number of choices, such as alignment of metal to gate. One option is to have the metal lines and gates line up where possible. The other is to opt for a design where the initial alignment line is midway between the gates underneath. “We call this the ‘M1 in-between PC’,” Ban said. “Each 3:2 configuration requires two library sets due to symmetry characteristics.”
Image Comparison of access-point choices in an AOI22 cell with different types of 3:2 layout
The placement engine needs to interleave the Type-A and Type-B cells so that it can maintain DRC-clean spacing for the metal lines. An open question is how routers and library designers will deal with the different cell options. A type-A cell of a certain width may have five metal lines passing over it while a type-B may only have four, which will necessitate different layouts which could have different levels of accessibility. This adds an extra degree of difference over and above the options for color-aware cells, demanding different layouts for Type-A and Type-B cells rather than simple reflections or rotations.
A further issue is tweaking the design rules to accommodate the differences in alignment between metal lines, poly contacts and vias depending on whether the metal lies halfway between the gates or slightly overlaps. “Via rules are much more important, V0 especially,” Ban said.
Analysis of pin-access opportunities by GlobalFoundries found that the in-between version allowed more pin-access opportunities as the 1:1 version and was likely to suffer less from multiple patterning constraints. The ‘M1 on top of PC’ version increased the number of pin access points on average but is less easy to manufacture, Ban said: “The via enclosure is very small and very challenging for patterning.”
On an OpenRISC 1200 processor-based test design laid out for a 13-layer metal stack, the use of 3:2 gearing led to cell area increasing by around 7 per cent the placed circuit turned out to be about 10 per cent faster. Part of this was due to improved source/drain resistance because of more relaxed design rules around the transistors but also because critical paths could be shallower thanks to apparent improvements in routability. As a result, congestion was lower than with a 1:1 gearing.
Ban said effective cell density improved by 8 per cent. As well as making it easier to route between adjacent cells, the 3:2 turned out to have an advantage when delaing with dense power rails. “Placement under a power rail is very difficult with 1:1. With 3:2, since the library has a higher number of access points, it is easier to place cells under the power rails,” Ban said.