With RF, power and MRAM, FD-SOI finds its role

By Chris Edwards |  No Comments  |  Posted: July 12, 2018
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , , , ,  | Organizations: , , ,

GlobalFoundries has claimed it has more than 50 design wins for its 22FDX process, which is based on fully depleted silicon on insulator (FD-SOI) wafers, that are expected to amount to at least $2bn when they go into production. After a long gestation, FD-SOI looks to be carving out several niches alongside the mainstream finFET process technologies.

Ahead of the Design Automation Conference (DAC) in San Francisco in late June, Arm said the company has developed a compiler for Samsung’s embedded magnetoresistive memory (eMRAM) module, which is available on the foundry’s 28nm FD-SOI process (28FDS) as part of a portfolio of IP for the technology.

Kelvin Low, vice president of marketing for Arm’s physical design group, said the company opted to build a compiler rather than offer fixed-size instances because of the variety of applications for the eMRAM technology. “We are focusing mostly on flash replacement at the moment,” he said but the compiler can target uses for replacing electrically erasable memory blocks and in data buffers and scratchpads where long retention time is not the chief requirement. Low said longer term, last-level cache replacement will become more important and is an area of active research among the FD-SOI foundries.

The compiler supports options to improve temperature robustness with the aim of supporting products, such as those in automotive, that will need retention at 150°C and error correction.

Body bias power cuts

Low noted that a key advantage for FD-SOI is its support for power tuning through real-time changes to the voltage applied to the transistor body. “FD-SOI without body bias doesn’t really make sense. With body bias, FD-SOI provides a lot more flexibility for threshold voltage and extend the range of operation,” he said.

Design for body bias increases the number of timings-analysis corners during signoff, with multiple combinations of process variability, voltage and temperature, Low said. “The number of PVT points we have to provide has more than doubled. Some designs have two hundred or so PVT points. But the design infrastructure is available: Cadence and Synopsys have flows that support body biasing on FD-SOI.”

In a panel at DAC organized by Synopsys in collaboration with GlobalFoundries, Kripa Venkatachalam, director of product management for the foundry said the “ability to do back-gate bias drives extremely powerful optimizations. It also drives novel circuit topologies thanks to the ability to alter Vt in silicon”.

In a test design based on an Arm Cortex-A53, Venkatachalam said compared with the older 28nm high-k metal-gate bulk-silicon process, the migration resulted in an 43 per cent power saving, with 11 per cent coming from the migration and the rest from body bias tuning.

Beyond power optimization

In May, VLSI Research CEO Dan Hutcheson warned attendees to the SOI Silicon Valley Symposium body biasing on FD-SOI risks being oversold, with project managers wary of the increased complexity of design.

Venkatachalam insisted the design process with body biasing is not difficult though the idea of “back-gate bias gives the impression of being complex”. She added: “We are seeing customers start from scratch with FD-SOI and take it to tapeout in less than six months.”

Jacob Avidan, vice president of R&D in Synopsys’ design group, explained how the company has implemented direct support for FD-SOI timing analysis in its PrimeTime tool and in its UPF flow. He insisted, thanks to application of interpolation techniques, the use of body biasing in combination with PrimeTime does not add extra corners. “In signoff with PrimeTime, you have to add a bias voltage but that’s the only change to the signoff environment. That lets you look at the tradeoffs between performance and power using different levels of bias scaling. We’ve done a lot of SPICE simulations and we are within 3 per cent in PrimeTime, which is inside the criteria for foundry signoff. You can interpolate any point along the line, which saves you having to generate a library with all these [different bias] points.”

Potentially more important, according to Venkatachalam, is the ability of FD-SOI to integrate RF and power circuitry based on LD-MOS transistors. “You can bring the PMIC into your chip as well, bringing components together into a single solution to drive cost down,” she said, adding that the foundry is working with design house and IP provider Verisilicon on a reference design for a single-chip narrowband-IoT (NB-IoT) node.

Venkatachalam said a design can incorporate low-loss antenna switches and use FET stacking on FD-SOI to cut down losses in the core circuitry. “You also have lower leakage with SOI,” she added.

Wayne Dai, president and CEO of Verisilicon, said: “The sweet spot is integrating RF. When you have an IoT node that can only cost a few dollars, you can’t afford to have the PA [power amplifier] outside.”

FinFET and FD-SOI choices

Dai pointed to the availability of eMRAM on FD-SOI as another advantage, providing a memory that is less susceptible to soft errors than SRAM. “We don’t need it to replace finFET [processes]. It’s a different market.”

Venkatachalam argued: “FinFET is the choice if we want to drive high density. FD-SOI has a role to play if you are targeting very low power and highly integrated designs that need RF and PMICs onchip.”

Dai added: “If you have a design with a very large digital requirement and it’s on most of the time at high performance, then finFET makes sense. But if you need high performance only 20 per cent of the time, then I think FD-SOI is a better choice, even for cellphones. FinFET is better if you want 4G or better. But we might consider FD-SOI for the low end.” He pointed to ADAS Level 2 subsystems as being contenders for FD-SOI. Level 4 on the other hand would probably require the performance of finFETs.

Venkatachalam added that GlobalFoundries expects it 22FDX to be a long-lived node and will add further process extensions. She also indicated there is a continuing role for the 28nm version. “All the customers who are moving from 55nm and 40nm will find a sweet spot in 28nm. It’s the best single-contact process,” she said, referring to the requirement for double-patterning in smaller geometries.

“22nm is the last node for double-patterning and 12nm will be the last for triple patterning,” Dai claimed. He pointed to 12nm as being a strong contender for millimeter-wave designs as those designs could be difficult to implement on finFET processes.

Low said FD-SOI “makes a lot of sense” for highly integrated LIDAR transceivers for automotive systems. The result is that FD-SOI is beginning to find its role in the market away from the mainstream process evolution.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors