DAC 2018 preview: Synopsys

By Luke Collins |  No Comments  |  Posted: June 18, 2018
Topics/Categories: Conferences  |  Tags:  | Organizations: , , , , , ,

Synopsys will have its usual strong showing at the Design Automation Conference (DAC 2018) this year.

Three events with foundry partners will enable visitors to understand the advantages of tight integrations between design tools, manufacturing processes and semiconductor IP when designing advanced SoCs

At breakfast on Monday 25 June, Arm, TSMC and Synopsys will discuss how they have been able to work together to enable optimized designs and faster design closure when creating SoCs that use Arm’s IP, targeted to TSMC’s latest processes.

The breakfast slot on Tuesday 26 June is taken up with presentations by Samsung Foundry and Synopsys, in this case focusing on the work they have done together to develop next-generation process nodes, and to enable the design of advanced SoCs on these notes. The publicity for this event suggests there will be discussions of both design successes at 10nm and a look forward to Samsung’s 7nm process.

At dinner time on Tuesday, things change gear slightly when Globalfoundries and Synopsys offer a series of presentations and a panel discussion focused upon using Globalfoundries’ 22DFX SOI process to build SoCs for IoT wearables and automotive markets. There will be more from Synopsys and partners on designing for the automotive market, and especially the rigours involved in meeting the requirements of the ISO26262 functional safety standard, on Tuesday lunchtime.

Synopsys will also offer updates on its tools, toolchain and solutions in a series of events throughout DAC’s calendar. On Monday lunchtime, the focus will be upon the Fusion Technology RTL-to-GDSII flow, with presentations from customers who are already using it.  Also on Monday lunchtime, there will be a series of customer presentations that explore the challenges of doing advanced analogue and mixed-signal designs on today’s complex finFET processes, especially for markets that demand very high performance and very high reliability. On Monday evening, Synopsys is also hosting a dinner for the PrimeTime Special Interest Group, focusing on golden timing, power and reliability sign-off closure. On Tuesday lunchtime the focus will be upon how Synopsys customers have been using its tools to verify increasingly complex SoCs.

To attend any of these events, you need to register via the pages linked above.

Synopsys will also be working with partners to run a series of presentations at its Silicon to Software Theatre on the show floor throughout DAC. Your interests will vary, but from a generalist’s point of view there seems to be a number of intriguing presentations scheduled at this venue, including:

  • On Monday at 3:30PM, Esperanto Technologies on “Automating Physical Design of an Energy-efficient Machine-learning Processor Using Custom Compiler Environment”
  • On Tuesday at 11:30AM, Helic, NVIDIA and Synopsys on “EM-aware Parasitic Sign-off Flow in NVIDIA Using Synopsys StarRC with Helic Exalto”
  • On Tuesday at 2PM, Samsung on “Machine Learning for Microprocessor Design and Verification”
  • On Tuesday at 3PM, Synopsys on “IP for AI SoCs: Addressing the New Challenges of Machine Learning and Deep Learning”, followed by Synopsys at 3:30PM by “Machine Learning for Verification”
  • On Wednesday at 2PM, Amazon Web Services on “Innovating at Cloud Speed for IoT, AI, and Semiconductor Design”
  • and at 2:30PM, TowerJazz on “Industry First Open Commercial Silicon Photonics Process”

Similarly, there are a number of presentations being held on Synopsys’ partners’ booths throughout DAC, as listed here.

Finally, if you are interested in the future of EDA, Synopsys will be participating in the DAC conference throughout the week. Highlights include:

A workshop on machine learning in design automation, running all day on Sunday, which will include invited talks, panels, tutorials, and posters given by five academics and three EDA industry speakers. The workshop preview suggests there are a couple of key issues to be explored at the workshop: whether the algorithms, heuristics and mathematical methodologies used in today’s EDA tools can be sped up by using machine-learning specific architectures; and the extent to which machine-learning strategies could be applied to EDA’s most difficult problems.

On Monday, Synopsys will continue its machine learning theme, chairing a session on hardware IP for deep learning, in the IP track from 10:30AM to 12PM, and a tutorial on machine learning for EDA applications, in the afternoon machine-learning track from 1:30PM to 5PM.

Synopsys’ involvement at the conference later in the week is listed at the following links – Tuesday, Wednesday, and Thursday  – and covers topics as diverse as evaluating silicon power consumption in different application-specific scenarios, and the prospects for inductance and EM effects to have greater impact on SoC designs.





Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors