EDA

Review highlights from Mentor's activities at DAC and grab your last chance to register for in-depth technical sessions.

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.

Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.

Startup Tortuga Logic has developed a toolkit for checking the security aspects of SoC hardware designs.