Two-day app challenge results in RTL power analyzer

By Chris Edwards |  2 Comments  |  Posted: June 11, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , , ,  | Organizations:

For DAC 2015 in San Francisco Invionics set itself the challenge of taking suggestions for an EDA tool on Monday that its developers could implement using the company’s custom-tool framework by 2pm Wednesday afternoon (June 10). The result was a static, language-agnostic RTL analyzer that could flag up lines of HDL and blocks likely to suffer from high switching activity.

The shift to finFET processes, which exhibit high gate capacitance and so suffer from high power consumption in high-activity cells and blocks, has highlighted the need for power prediction that focuses on switching behavior. So, the idea provided by Daniel Hoggar of New York Digital Design picked up the most votes at the show and was given as a task to Invionics’ developers at their Vancouver HQ. Forty eight hours and three prototypes later, delivered to CEO Brad Quinton and colleagues at the show so they could tune the interface and behavior, they were able to show the tool running on the booth.

Demonstrating the tool, Quinton said: “It’s designed to provide quick feedback on your power architecture without needing a testbench or synthesis. It’s a static tool that uses probabilities to set how likely the gate’s output will be in a one or zero state and its probability of change [per cycle].”

Clock separation

The tool analyzes the HDL and is able to pull out clocks so it can assign default state and switching probabilities to them. Based on the probabilities, the tool then displays a block-by-block heat map and also color-codes individual HDL statements. The colors shift from deep red for high-activity signals with a high fan out through pink for moderately active signals to dark blue for those that rarely change and with few downstream gates.

Quinton said designers could use, and customize, a tool like this to see how to rework logic to reduce fan out on high-activity gates or minimize activity by reducing their overall toggle rate. “If you AND low and high toggle signals, the result will be a low toggle-rate output whereas other architectures may allow high toggle signals to ripple through.”

The tool could switch between a variety of HDLs using built-in parsers based on Verific’s technology to produce a high-level netlist ready for analysis using GUI elements provided by the development environment. “The exciting thing was we did it in 48 hours without really knowing too much initially about the problem space.”

Quinton said the company expects to add the tool to the examples that ship with its development environment.

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