Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
EDA
Menta aims for TSMC 28nm with embedded FPGA cores
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
Debug monitors look for deadlock
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Flow exploration key to finFET network processor implementation
Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
10nm flow reveals complexity of finFET design process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
PSpice builds interfaces to PCB and system-level cosimulation
The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
Chipmakers see 3x test-pattern saving in embedded-test logic
Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
FastSpice update improves parallelism and adds wreal support
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Sonics updates tune memory and link width for speed and power
The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
Tanner integration to assist Mentor in IoT and photonics
Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.