Collaboration let HiSilicon accelerate 16nm finFET plans

By Chris Edwards |  2 Comments  |  Posted: June 16, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , , , , ,  | Organizations: , , ,

Last year, HiSilicon became the first company to reach product tapeout on TSMC’s 16nm finFET process, moving up from its status as fast follower to being in the vanguard of process adoption. In a panel organised by Cadence Design Systems, the company’s director of R&D operations put it down to a combination of restricted resources and cross-industry collaboration.

“We are lucky to be the first one to tape out the first 16nm chip in the industry,” said Yanqiu Daniel Diao, deputy general manager of HiSilicon’s network processor business unit director of R&D operations.

Diao explained: “The original plan was not to take that risky path. The original plan was to take more of the safe side and do four projects in a sequential manner. First we aimed to do a 28nm test chip, then the 28nm pilot, followed by a 16nm test chip and the 16nm pilot.

“We knew sooner or later we would use 16nm – my department is doing processor design, so we’re first to use high technology within HiSilicon. But we didn’t know that the day would be so soon. We have limited resources in back-end implementation. Doing four projects: we would be very limited in our design resources. So our president said we can’t do that but we should combine those four into just two.

Runtime increases

“We faced a huge challenge,” Diao said, acknowledging issues mentioned by other teams working on finFET designs around manpower and compute-resource requirements to deal with tens of corners during signoff and switching-power reductions.

“All those challenges are very true. But for us the big challenge was that of uncertainty: how to do a tapeout in new technology that no-one has done successfully previously. We engaged the benefits of being followers before. Others did successful tapeouts before us. And we had access to mature EDA tools and libraries. The biggest challenge was this one.

Diao continued: “We had to set up organization that could deal with that challenge. Using the sequential approach, we could put much more human resource on this project. Because of the double patterning many more engineers need to be put on the projects. We put much more computational resource into this project. We almost tripled the the resource compared compared to resources used for 28nm project.

“But we had close collaboration with TSMC and EDA, that’s the most important thing. At the foundry we had a close partner in TSMC and close EDA partners in Cadence, Synopsys and Mentor [Graphics]. They supported us to cross that chasm. To do finFET, you need that three-way close collaboration.

“The close collaboration between design team and foundry and EDA tools and IP providers are more and more important in the future. We see the importance of this even more as we move to 10nm. The trend that will not change is that collaboration at the early stage and R&D level. And very quick response times between each partner are becoming more and more important,” Diao argued.

16nm choices

Having completed its first foray 16nm finFET, HiSilicon expects to follow with more designs but expects many existing types of product to stay on older processes. “We want to put more projects on 16nm finFET to see the benefits of performance and also power. But we are very careful about the limitation of the IP availability on 16nm finFET. That’s a very key factor on selecting projects that can use 16nm finFET.

“Not all our projects are suitable for 16nm,” Diao explained. “Currently we only have processors in networking and also high-end mobile processors. All the other designs are still on older technologies.

“We provide most of our designs to our parent company, which makes telecom equipment. Most of the core network requires very high performance and power is also is really a limiting factor. That pushes us to use 16nm finFET.”

But finFET design and products come with a higher price tag that offsets some of the scaling advantages, Diao added: “Cost will go up. The cost of the chip and also computational resources. But if you chose the right areas that can see the benefits, after a calculation, you can do it with confidence.”

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