EDA

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.

Siemens is integrating the Supplyframe platform with the Xpedition PCB-design software to give engineers better visibility into component availability.

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.

A comprehensive review of ML's potential and its current use identifies challenges ahead.

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.