Reset domain crossing is a difficult and time-consuming verification challenge. A paper originally presented at DVCon Europe 2020 has been made generally available that describes an advanced methodology that can be incorporated with a necessary static verification tool.
The methodology addresses not only the complex steps within the reset domain crossing task during any necessary static analysis but also reduces the noise that makes existing strategies still more time consuming. “This is achieved through proactive functional analysis of reset assertion sequences of complex combinational reset logic that drive RDC crossings,” explain authors Milanpreet Kaur and Sulabh Kumar Khare from Siemens EDA.
Importantly, the methodology is deployed to RTL and before gate-level verification where reset domain crossing failures can lead to respins, Reset domain crossing has become a more pressing issue because of the use of multiple interfaces and multi-mode operational states that have increases the number of reset sources found in today’s system-on-chips.
The Siemens EDA paper, ‘Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection‘, validates the proposed methodology through a case study using a complex SoC with more than 1.8 million registers and five RAMs.
In its real-world use, the methodology concentrated effort on “the relevant unsafe RDC paths and helps users focus on verifying them effectively,” the authors confirmed.
“Several scenarios depicted in the paper ensure no critical path is missed and false crossings are reported. Advanced techniques utilize reset ordering information as well to simplify the reset architecture and enhances the tool capabilities,” they add.