Chipmaker

Arm is to return to focusing on semiconductor IP following the decision to spin out its IoT operations to separate groups within the Softbank empire.

The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.

Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.

Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.

Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.

Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.