Chipmaker

Arm has put together a program based on its existing Flexible Access model that is intended to provide early-state startups with a broader list of cores they can prototype before needing to take out a full licence.

Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..

Mythic will use the Mentor tools for its analog-targeted intelligence processing units.

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.

SureCore has started running 30-day trials of its low-power memory compiler.

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.