ARM completes multicore test chip on 10nm finFET
ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
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Functional safety and high reliability for FPGA designs – eight videos show you how
Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
Allegro release tackles new generations of PCB
The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.
Cadence boosts MAC count for neural networks
Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.
Toward easier, faster test pattern simulation
Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.
User2User preview: Silicon Valley edition rolls out this month
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
SNUG 2016: Aart de Geus looks beyond the linear design flow
Do the synapses in the human brain offer a new model for the design flow in a Smart Everything world?
SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
Cadence moves into safer design with Virtuoso changes
Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
HyperLynx made broader and easier to use
HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.