Allegro release tackles new generations of PCB

By Chris Edwards |  No Comments  |  Posted: May 3, 2016
Topics/Categories: Blog - PCB  |  Tags: , , , , ,  | Organizations:

The latest release of Cadence Design Systems’ Allegro PCB design environment builds in tighter connections to the Sigrity signal-integrity tools as well as functions intended to speed up design for flexible and mixed-substrate circuit boards.

The 17.2-2016 release also provides a mechanism to allow multiple designers to work on routing without having to partition the board first.

“The design rules for flex are very different to those on a rigid board,” said Hemant Shah, group director of product management in Cadence’s custom and PCB group, adding that for teams dealing with mixtures of flex and rigid boards in a system design are spending 80 per cent of their time on the flex portion using existing tools.

Designers need to ensure that components are not placed too close to a bend to avoid their pins peeling away from the substrate. And the routes themselves tend to use more curved sections, Shah said.

“Plus there is a whole set of different layers and surface finishes that come into play,” Shah said.

Layer matrix

Although designers can employ user-defined layers in existing tools, Shah said: “What we did was come out with a way to specify what they have using a matrix. You click the combination you want to use and define the gap and overlap rules that you want. As the layers are defined we flag what will be the design-rule violations. We have made it extensible so the fabricators don’t have to wait for us when they come up with a new layer definition.”

On rigid boards the increasing use of material inlays also complicates design-rule handling. Shah said companies are now taking advantage of manufacturers’ ability to carve away sections of FR4 and replace them with higher-quality materials such as Rogers to support RF transceivers and other high-speed circuits. This reduces the cost of using the more advanced materials compared to building the system completely on them. Design rules need to take account of copper routing around the join and to prevent components crossing over a boundary.

Concurrent design

Shah said the call for denser routing and the shift to DDR3 and DDR4 buses has put more pressure on routing and increased design time. Dividing the effort among multiple engineers provides one way to cut the time to completion, he argued.

“We had split and merge before. It required some structures so we’ve made it simpler,” Shah said. “There are two modes. One is a casual, ad hoc mode. The first person to start owns the design on their machine and the changes made by other engineers are synchronized to it. The second mode, typically for large designs that they want to be backed up, is where they set it up on a server first.”

The synchronising scheme works by locking to each engineer the element they are working on at any one time, which could be a simple route or a defined bundle such as a DDR byte lane. Shah said the system reliably handles five concurrent sessions but that some customers had pushed it further.

Integrity checks

The closer integration with Sigrity makes it possible for signal-integrity engineers to work on portions of the layout and have them carried over to Allegro using XML files that the layout engineer imports. The Sigrity tools also now understand complex layout shapes such as tabbed routing that some design teams are using to control signal-line impedance. Tabbed routing makes it possible to employ some of the otherwise useless space between BGA pads for tracks that run between them in the orthogonal direction.

“A typical signal-integrity tool analyses it all as a shape, which is more time-consuming than understanding that they are tabs,” Shah explained.

Support for via structures lets the signal-integrity engineers work out how best power and ground vias should be placed around sensitive differential pairs and export the entire structure for use in the actual layout. This avoids the need to have a set of round trips between design and simulation as the structure is refined.

“Another issue is back-drilling,” Shah said. “We have supported back-drilling for many years. We are adding new rules to make it easier for designers to work and correct errors as they are made. The back-drilling clearances are shown on the design. And when they give it to Sigrity to simulate the effects, it calculates the impact of the little stub left in there rather than a full stub.”

Other visual feedback for the layout engineer comes in the form of routes that are color-coded according to predicted IR drop. “The time to sign off is shorter because the work is already done by the PCB designer,” Shah claimed.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors