Verilog-AMS release adds to power-aware analog modeling
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Archives
Applications won’t find all the bugs, but they have their uses
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
Intel’s security architect lays out protection plan
At DAC 2014, Intel’s chief security architect Ernie Brickell described the processor maker’s approach to protecting hardware and software from hacks and attacks.
eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond
Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling
EDA industry must look to new markets for growth – Rhines
New markets such as hardware cyber security, automotive and embedded software key to EDA industry growth
3D and EDA need to make up for Moore’s Law, says Qualcomm
Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.
Remember 20nm? Qualcomm does
Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
Chipmaking’s future: all of the nodes all of the time
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible - the idea is familiar but how do you get there?