Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group continues toward a planned merger with SystemVerilog. This will combine the numerous analog representations of AMS with the more digitally oriented wreal/real-number enhancements introduced by the 2012 version of SystemVerilog.

Version 2.4 contains a number of corrections to 2.3.1, the previous release, as well as new examples and features to support power-state modeling, such as an easier way to represent changing supply voltages, as well as other enhancements for compact modeling – introduced in version 2.1 – and behavioral modeling.

Verilog-AMS was first released in 2000, being built on top of IEEE 1364 Verilog before it was subsumed into the SystemVerilog standard. The standard defines how continuous time models of analog behavior interact with event-based representations.

“Verilog-AMS 2.4 is the result of the hard work and collaborative effort of the Verilog Analog/Mixed-Signal (AMS) working group who came together to deliver this standard,” said Scott Little, chair of the Verilog AMS working group. “This revision adds several features that users have been requesting for some time, such as supply sensitive connect modules, an analog event type to enable efficient electrical-to-real conversion and current checker modules.”

Little said future work would incorporate Verilog-AMS into SystemVerilog, which now has support for mixed-signaling modeling based on real-number, discrete-event representations, recently adding functions such as ‘nettype’, which allow for user-defined modules to determine the voltage on ports that may be driven by both digital and analog circuitry.

Release 2.4 of Verilog-AMS is available for free download from Accelera’s website.