eSilicon to cut costs of ASIC development for IoT, other markets

By Luke Collins |  No Comments  |  Posted: June 6, 2014
Topics/Categories: Design to Silicon, GDSII, Blog - IP  |  Tags: , , , ,

eSilicon has introduced two online tools alongside its multiproject wafer quotation service, in a bid to make ASIC design more accessible and cost effective.

The move comes as it becomes apparent that for many companies, the future of chip design will involve making repeated optimisations to 28nm designs and their supporting logistical flows to achieve the power, performance, area and costs they need, rather than making the leap to finFET processes

At DAC this week, Jack Harding, co-founder, president and CEO of eSilicon, said: “My belief is we will automate the ASIC development process online. I’m not going to tell TSMC how to make wafers, or EDA companies how to make tools. I am going to tell people how to access those wafers and those tools.

“This leads us away from just running to the next node, towards more power, performance and area-conscious design.

“Because of the increasing cost per gate [of the latest processes] people are saying that we shouldn’t sprint to the next node, but should walk there thoughtfully and see what other improvements we can make along the way.”

Harding argues that one such improvement is to make it easier for chip designers to explore design and production options without financial commitment.

eSilicon launched an online tool to enable users to explore using a MPW service to trial their chip designs in October 2013. To date, Harding says, 200 institutions have used the tool and the company has provided 600 quotes. He says the availability of the tool has led to a couple of million dollars of revenue and some good profitability.

“Half of the users have been at companies we’ve never heard of in countries that we have never visited,” he said, adding that the use of the tool had given eSilicon insights into the IP and the processes that these potential new customers are interested in using.

“Do I want to give the sales people the name of some guy who stopped by our booth for a squeaky toy, or the name of someone using a specific piece of IP on a specific process?” he said. “Early returns give me hope that there’s a monetisation opportunity there.”

To follow on from the MPW tool, eSilicon has this week launched two other online tools with which designers can explore design and delivery options. The first is IP MarketPlace, through which users can configure eSilicon-designed, compilable SRAM IP blocks.

“We decided to look at other parts of the chip than the domain of RTL and EDA,” said Harding. “Is it better to squeeze the last 2 or 3% out of RTL through the use of tools or attack the problem from a different angle? So we looked at memory, where we can reduce power by 30% and area by 5 to 20%.

“Without forcing customers to move beyond 28nm, we’ve been able to give them the post-28nm experience with less cost, lower risk and greater predictability.”

Alongside the SRAM configurator, eSilicon has also announced a GDSII portal through which customers can explore various options for taping out to TSMC processes, such as packaging, testing and delivery, at no cost. At the end of the configuration process, eSilicon will offer the user a unit price, and commit to yields, NRE, test times and so on.

“Without ever having spoken to a human being, we’ll commit to a complete economic engagement,” said Harding, adding that with the average GDSII tape-out being worth $750k, the portal may end up having some of the highest-value transactions in ecommerce. “And now you’ve got competitive analysis online.”

The fact that eSilicon will offer pricing without a commitment from the user doesn’t phase Harding.

“Our SRAM approach is well understood but the ecommerce is a leap of faith,” he said. “I don’t know how to monetise this. But I do think we’ll build a community, strengthen the brand and create the opportunity to upsell.”

Harding argued that eSilicon’s efforts to automate key stages of the chip design and delivery process could work well for emerging markets, such as devices for the Internet of Things (IoT).

“IoT is not a semiconductor issue,” he said. “It’s the intersection of cloud computing, massive ecosystems and finally, the semiconductor industry.

“That doesn’t mean that there isn’t an opportunity to ship trillions of transistors into that market, but the chip makers won’t be in charge.

“When I think about IoT, I think about online design of relatively simple chips. I believe the automation track we’re on could provide a fruitful ecosystem for a cottage IoT design industry of people putting chips in sneakers and purses.”

Harding added that eSilicon’s Internet activity is teaching the company about a group of people who want to do substantially less complex designs.

“Lots of companies like NXP and Atmel are being labelled future leaders in IoT,” he said, “but I think there’ll be an equal amount of innovation coming from the bottom up, creating an opportunity to service them.

“Will we be able to enable new companies to participate in the semiconductor industry, those who have been marginalised by the move to newer nodes, and the new entrants?”

He argued that over the past 65 years, early adopters of technology have paid heavily for the privilege of access to tools and techniques that later become commonplace.

“Is it now safe to imagine that the ability to develop a semiconductor can also become ubiquitous and put in the hands of anyone with sufficient vision to explain an idea? I don’t think that is far fetched and history suggests it is inevitable.

“I’m not sure where this is going but we’re the leader in doing it.”

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