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Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.

The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.

Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.

June's Symposia on VLSI Technology & Circuits will bring together a number of industry trends that extend from implantable biomedical applications to machine learning and cloud computing under the banner of technologies for ‘smart living’.

Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.

Accellera Systems Initiative has begun a project that may result in the creation of a standard to address security assurance for semiconductor IP cores.

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.