Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Archives
Motion harvester wins MEMS design contest
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
Cadence opens three fronts on mixed-signal failures
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Combining tools and services for evolving automotive design flows
Automotive companies need to partner closely with tool suppliers as design processes are disrupted by new technologies.
Anne Cirkel recognized for advancing role of women in electronics design
Mentor executive, former Design Automation Conference chair and Tech Design Forum journal founder to receive Marie R. Pistilli Award at DAC 2018.
Free formal verification primer offered by Synopsys
Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
Tensilica DSP extends pipeline for performance
Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.