Kioxia looks to waferscale flash drives for fast, low-cost storage
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
Archives
How Ambarella met the demands of automotive DFT
Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.
Siemens raises Capital to full E/E design level
Capital has been grown from a wire harness suite to a full electrical/electronic platform with integration for digital twin strategies.
EDA in the cloud boosts DRC iterations for AMD
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Onchip sensors aim for finer-granularity heat measurements
Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
Real Intent tries to shift left on DFT
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
IEDM plans for San Francisco in December
The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.
Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Parasitic extraction to guide capacitor usage in RF SoCs
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
Coronavirus Resources: Mentor
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.