Real Intent has updated its Ascent X-Verification System (XV) to improve it ability to analyze the initialization of designs when unknown (X) states are present, and to detect and manage those X states.
Graham Bell, vice-president of marketing at Real Intent, said: “Ascent XV provides the necessary analysis of initialization sequences to ensure they are complete and optimal for various power states in an SoC.”
The X verification tool identifies X-sources and potential X-propagation issues in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, in which the impact of X states is underestimated, prior to synthesis. It also eliminates unnecessary Xs at the netlist level that are caused by X-pessimism, in which the impact of X states is overestimated.
The tools’s initialization analysis feature reports any flops or latches that remain uninitialized after the reset sequence. It will also optimize reset and retention flops to ensure complete initialization with minimal hardware and routing resources. Hazard analysis reports design susceptibility to X-hazards, and automatically detects and reports all X-sources in the design.
The tool also includes a SimPortal, to enable Verilog simulation to detect and debug real X-optimism issues, and to model low-power retention cells at RTL.
A debugger is available to correlate X-optimistic and X-pessimistic signals to X-sources.
See a video of Pranav Ashar, CTO at Real Intent, about Ascent XV and the need for X sign-off, here.