Stepping up
During the CEO Panel at this year’s Design Automation Conference, the men leading the three largest EDA vendors stressed that their industry can do well in a slump because it both contributes to the ongoing battle against technological limits, and enables the delivery of ever greater efficiency. But another, parallel question raised by this year’s DAC and by today’s broader semiconductor environment is, “Just how much can EDA do for semiconductor vendors?”
The point here is not to highlight the limits of design software, or even, as has been previously suggested, ask whether the vendors should limit their horizons to give clients room to differentiate products. Rather, we need to concentrate on the broad and—more pointedly—blunt issue of the fabbed, fabless or sub-contracted design manager.
One of the great economic advances enabled by EDA recently has given ESL abstractions the capability to underpin more easily executable and financially quantifiable designs. Identify both your goals and your main problems early on and chances are you will get to market quicker and more profitably. Yet, even allowing that ESL has varied in its adoption rate across both geography and sector, the overall respin rate remains worryingly high.
IBM fellow Carl Anderson gave an excellent but alarming speech at DAC during a session previewing the 22nm node (see page 38). There is a plethora of tools and the tightest constraints in terms of time and money, but a common reason for major project delays remains late stage changes. When a project manager must decide whether to stay the course or make concessions, he all too often strays too far down the latter course, incurring risks that history tells us usually do not pay off. For these circumstances, Anderson offers an interesting challenge: “innovation inside the box.”
Tools can only do so much—the responsibility comes down to the manager and the team wielding them. What is needed is a combination of craftsman, creator, professional and military general. Anderson had a slide showing both Albert Einstein and George S. Patton, the point being not so much the comparison as the characteristics each represents for different aspects of the industry.
The issue goes further. For example, we are on the cusp of a new age of systems-in-package (SiPs) technologies as an alternative to monolithic integration within systems-on-chip (SoCs). However, those who believe SiP is simply a poor man’s SoC are deluding themselves. One design company describes the comparison more as “entering the world of relative pain.” There are good reasons why TSMC has only just added SiP to its Reference Flow, and so far qualified only one EDA vendor, Cadence Design Systems, which itself remains cautious about the road ahead. And why—because, as you’ve guessed, the SoC vs. SiP decision is a lot tougher than we have been led to believe, and success will depend on the commitment design managers are prepared to show throughout a project’s life.
Tools can and will do an awful lot, but now more than ever, Spiderman’s Uncle Ben was bang on the money: “With great power, comes great responsibility.”
