RISC-V

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.

Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.

Mentor, a Siemens Business, will offer a broad range of technical and market insights at the event – as well as a free virtual coffee for those who visit its virtual booth at the show.

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.