Breker packages up apps for RISC-V, security and AI

By TDF Staff |  No Comments  |  Posted: July 21, 2020
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations:

Breker Verification Systems has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.

For RISC-V, Breker has created what it calls a TrekApp for cache-coherency verification, seeing it as a key concern for more advanced RISC-V deployments. In addition the company has added mechanisms to the check behaviour of other elements needed for processor integration such as interrupt handling. Breker has worked with customer SiFive, which specialises in RISC-V processor design, on the TrekApp.

Working with another, much larger semiconductor company, Breker has developed a TrekApp for security checks. This performs the automated verification of protected regions on an SoC. It essentially performs a semi-formal synthesis operation, constructing an SoC state space from the security rules provided by a set of tables. The resulting code is then parsed by Breker’s synthesis technology to produce simulation and emulation tests that check all possible vulnerable accesses to registers and memory in the region.

For machine-learning applications, Breker has worked on issues that affect convolutional neural networks. One problem is that a small error in a node can propagate throughout the network and generate a much larger error at output. The company has developed an approach that uses generated graphs to capture those types of error.

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