Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
RISC-V
DAC keynotes and sessions aim for AI
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
UltraSoC delivers trace for RISC-V
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Codasip updates processor-architecture tools
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Workshop sees the RISC-V ecosystem expand
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
Microsemi sets up RISC-V partner program
Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
Codasip adds IoT core to RISC-V line
Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.
UltraSoc donates trace format to RISC-V group
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Microsemi builds Windows IDE for RISC-V
Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.
Open-Silicon claims RISC-V ultra-low-power first
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
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