RISC-V

Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.

Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.

Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.

Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.

A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.