RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.

The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.

Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.

OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.

The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.

OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.

The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.

Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.