Double patterning and finFETs are on the horizon. Until production starts, EDA companies such as Synopsys are having to plan for the different ways in which these technologies will be used as their yield information becomes available, Antun Domic, senior vice president and general manager of the implementation group at Synopsys, explained during an interview with Tech Design Forum at the DATE conference on Wednesday.
“There are a lot of concerns because of the introduction of double patterning (Guide). It’s a little too early to tell but it looks to us that the problem of double patterning has been handled well. There has been a lot of work in routers and layout verification tools, and a lot of work in libraries. My feeling is that things are under control,” said Domic, pointing out that the core design methodology has not been changed by double patterning. “We are not seeing things that are telling us that there is something dramatically different in terms of design methodology. But no-one has any data yet on yields.”
Until production shifts into high volume on 20nm processes, it remains unclear whether double patterning will demand additional attention from circuit-level designers. The key question is: do you need to control how metal lines will be split across masks? If not, it’s largely a tool problem. If process variations caused by different traces being imaged by different masks are large enough, it may mean analog designers having to decide to keep certain traces on the same mask – and colored identically in a tool – to maintain good matching.
“There are still two schools of thought,” said Domic. “There are some people who would like to color themselves. Even in digital cells we have had two schools of thought over this. We have had to support both options. Until some level of production is seen and we get some level of stability in the process, it is hard to tell which will prevail. if variability persists then people may need to preserve the colours.
“Similarly, there was an issue of misalignment of masks. We had to propose a new standard for extraction to deal with this. However, the current feeling of the foundries is that the alignment is being controlled better than expected. So it looks as though this type of extraction is an option rather than mandatory. If foundries are able to control this variability, it will not be needed.”
If extreme ultraviolet lithography (EUV) suffers more delays, double patterning may only be the start. The industry may have to shift to self-aligned multiple-patterning approaches on the way to directed self-assembly – forcing a move to more regular layout styles.
“What we will see is a more disciplined approach to the design of circuits and memories,” said Domic. “If not it’s far too complicated. From the point of view of certain areas like RTL and logic synthesis, these things are not even seen by these tools. If you look at the success of the industry overall, it is based on a highly productive cell-based design methodology. With extra work we can preserve the characteristics of this methodology. When I look at chips with five billion transistors there is no way we can go to very detailed design analysis.”
A further area of uncertainty is what happens in the transition to finFET-based processes (Guide). As 20nm has yet to ramp up, widespread production of these processes outside Intel is further out. However, the foundries have accelerated development of finFET-based processes.
“People are trying to bring in finFETs much earlier because the technology offers power and performance advantages,” said Domic.
“The good news is that, at least from a foundry perspective, the wiring where double-patterning issues appear will be very similar to 20nm. That work has been done. So the work is about making sure that the libraries and tools are available for the finFET devices.
“The IP group working with cell libraries and other IP. My feeling is that the EDA will be ready for the finFET transition. Synopsys will be ready definitely,” Domic claimed. “Design could become a little easier. With finFETs, leakage will reduce. That will simplify a lot of the optimizations that get done today. For example, we see people using four variations of a cell because of leakage challenges with CMOS. It may be they will need fewer variations because of the lower leakage of the finFET.
“With extraction, there are two areas that require particular work. One is models for transistors. With the fins there are new parasitics that need to be modelled but you have to decide whether some parasitics should go into the transistor model or whether StarRC has to extract that and put it into the parasitic net list. DRC and LVS also require more work but it’s not dramatically different from what people did before. The IP work has involved a lot of redesign.”
Because the finFET program has been accelerated at the major foundries, there is a question as to whether customers will opt to migrate to 20nm or wait and jump straight to the finFET processes to obtain their performance benefits.
“Some people are thinking of doing that,” said Domic. “I believe the final decision will be taken when the timescale for finFET becomes more firm. People will want to see the ramp-up curve.”
Some aspects of finFET-based design will have to wait for more information about the capabilities of the processes to become available. For example, fin spacing may turn out to be controllable – which will allow greater flexibility in design.
“Analog guys may want wider spacing on fins in some cases,” said Domic. But process decisions to be made by foundries may lead to fixed fin spacing with less control available to the custom designer. “We have still had to do work on fin spacing on the the basis that these things may be possible.”
This is the first half of an interview held at DATE. The second half will look at the how advanced tools are feeding back into mature processes