FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

By Luke Collins |  No Comments  |  Posted: June 5, 2013
Topics/Categories: Blog - EDA, IP  |  Tags: , ,  | Organizations:

The evolving needs of the mobile computing and communications sector are forcing foundries to make a series of delicate trade-offs in the development of their finFET based processes.

Not the least of these is the balance between process optimisation and process availability.

According to Subramani Kengeri, vice president of technology architecture in the office of the CTO at GlobalFoundries, “The mobile market is interested in finFET so we wanted to get finFET processes into customers’ hands at minimum risk.”

For this reason, GlobalFoundries’ 14XM finFET process uses its 20nm process’s BEoL and MOL, which together account for about 90% of the overall process’s design rules. The FEoL is at 14nm.

“The whole focus of bringing up the finFET process was on the device itself,” Kengeri said. “Our whole idea was time to volume, optimised for mobile computing.”

He added that the increasing use of graphics in mobile devices is causing a shift in the optimisation criteria for processes. In three to five years’ time, he says, 30 to 50% of a mobile chip’s area could be dedicated to graphics, so process designers need to optimise ultrahigh-density and low-power standard-cell libraries, a different set of criteria than have been used to date for more CPU-led designs.

The pressure to make a process available has also led to innovations in its development. The PDK that goes with the company 20nm planar process is “more or less usable” with the 14XM finFET process, so lead customers have been exploring it before its PDK is anything like mature.

“Unlike at any time in the past, where customers waited for the PDK to reach 1.0 status, we went to concurrent design and implementation.”

Kengeri says that the maturity of the physical part of the 14XM PDK is about at version 0.9, while the electrical part is “less mature”. If maturity is measured by how close the device is to the target AC and DC electrical characteristics “we’re within 50 to 60% of those, and once you reach that point, from there on it is easy.”

Kengeri says yeield is ramping as expected, and the company expects to offer the 14XM process for risk production in the second quarter of next year, “but designs and tapeouts will happen much sooner, because the process is leveraging the maturity of the 20nm process. Customers wil be ready to tape out designs six months ahead of risk production.”

IP development is also happening quickly for the same reason.

“This is the first node at which process, IP and customer design development are happening concurrently. That was the whole strategy and it is working really well,” said Kengeri.

Is there a ‘true’ 14XM to come? Kengeri says the 14Xm process already gives the power, performance and area advantages that customers are looking for. Moving to a 14nm process with a more aggressively scaled metal stack would mean using double patternign lithogrpahic techniques (Guide) on more layers, increasing cost and production cycle time.

“If you only use two or three double patterned layers, rather than six or eight, there are big differences.” Kengeri said. Couple this with the finFET performance advantages and he clains that you have reached the “sweet spot” for mobile computing.

“28nm was a sweet spot and the industry will pause on 14XM for a while,” he added.

The node after 14XM will be a ‘10nm’ process. Kengeri says GlobalFoundries’ advanced technology architecture group finished specifying the architecture of the process a few weeks ago, focusing on technology trade-offs.

“If you just scale everything by 0.7, that doesn’t work,” he said. “The real question is, what is the value at the SoC level?”

So, for example, the 20nm process has a 90nm poly pitch, because to go to less than 80nm would involve the use of double patterning. Fin pitch is 48nm, with a 64nm first metal layer pitch, to enable optimal standard cell layout.

“On 10nm, we have looked at all these factors again.”

Kengeri said that ensuring reliability at advanced nodes means looking at back-end issues, such as dielectric breakdown, as well as the usual front-end issues: “If you thicken the oxide to get reliability you lose the performance advantage. Beyond that, there’s another level of reliability in manufacturability, when you push the process’ design rules too hard to get the density.”

GlobalFoundries’ response has been to look at the standard-cell libraries its is implementing, finding the widely-used, repeating structures and then optimising them to gain density. Kengeri said focusing on these ‘constructs’, which are almost like a standard-cell library for building standard cells, lets designers push the process deisng rules intelligently, as they can in an SRAM cell design, because they know that they are regular structures.

“When you push the rules intelligently then you’re not pushing reliability limits, but taking care of them,” he said. “In 20nm, yield issues happened because people pushed the rules too hard.”

FinFET processes face another reliability issue which can only be addressed through design tradeoffs. The channel of a finFET experiences 1.8 times the current density of a planar transistor of the same planar area. This can create electromigration (EM) and reliability issues if the cell’s ground rules don’t support wider metal lines that can drive the transistor without suffering EM.

“Our ground rules support wider metal for power rails, without sacrificing density,” said Kengeri.

He said that the company’s 10XM process is currently scheduled to enter risk production at the end of 2015.

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