design management

October 17, 2018

FPGA playing verification catch-up as bugs escape

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,
January 23, 2018

Triage without tears: improving debug’s most human challenge

Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations:
December 13, 2017

IC Manage expands big-data work

IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 27, 2017

Cliosoft aims to bring cooperation to design management

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
June 8, 2017

DAC 2017 preview: OneSpin

Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
May 30, 2017

How Mentor realized concurrent engineering for PCB design

The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
May 17, 2017

Matlab links up with Virtuoso for circuit analytics

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.
December 4, 2015

Three key ways to reduce silicon test costs

Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
August 6, 2015

Flow exploration key to finFET network processor implementation

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
June 11, 2015

Data mining tools trawl for IC icebergs

Dassault Systèmes and IC Manage have each developed "big data" mining software tools to track the progress of chip-design projects
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,

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