Verification

December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
November 3, 2020

Showing ‘equivalence’ to seed digital twin adoption

A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
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October 29, 2020

User2User sets virtual 2020 dates: US in November, Europe in December

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
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October 27, 2020

ROHM eases component choice by offering cloud simulation and collaboration environment

A Japanese component supplier is making it easier for its customers to choose the right parts for their designs by offering a powerful analog and mixed-signal (AMS) simulation environment through its website.
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October 22, 2020

Mentor and Arm collaborate on RTL verification reviews

Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
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September 21, 2020

Deliver RFIC reliability and performance through automation

Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.
July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
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July 20, 2020

FastSPICE upgrade boosts nano-scale analog verification by up to 10X

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
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