Verification

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.

A Japanese component supplier is making it easier for its customers to choose the right parts for their designs by offering a powerful analog and mixed-signal (AMS) simulation environment through its website.

Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.

Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.