Verification

The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.

Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.

Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.

The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.