Verification

May 19, 2021

Understand how DO-254 defines verification for avionics

The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
May 13, 2021

Siemens extends Solido’s reach into IP validation with Fractal

Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
January 27, 2021

How to simplify ESD verification with pre-coded checks

Electrostatic discharge verification is becoming increasingly hard to achieve but automated pre-loaded checks can now help.
January 22, 2021

How to use virtual mode in emulation

Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.
January 14, 2021

A new methodology addresses the increasing challenge of reset domain crossing

Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
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December 18, 2020

Virtual emulation delivers verification for the latest storage devices

Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

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