Verification

February 12, 2020

AI processor company opts for Analog FASTSPICE and Symphony

Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
January 29, 2020

Toward more efficient formal strategies for deadlock

Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
January 28, 2020

Earlier latch-up prevention with topology-based analysis

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
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December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
October 7, 2019

Master the design and verification of next gen transport: Part Four – emulation

Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
October 4, 2019

Master the design and verification of next gen transport: Part Three – functional safety

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
October 2, 2019

Master the design and verification of next gen transport: Part Two – high-level synthesis

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
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July 27, 2019

A repeatable methodology for modern reset domain crossing issues

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.

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