Verification

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.

Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.

5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.

Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.

CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.

Variable lifetimes are an apparently basic but also tricky feature within the verification language.