Verification

High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.

Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.