3D-IC cooling ascends the agenda

By Paul Dempsey |  No Comments  |  Posted: April 10, 2013
Topics/Categories: Design to Silicon, Blog - EDA  |  Tags: ,  | Organizations: , ,

DARPA, the US defense research agency, believes that the heat dissipation requirements in stacked 3D-ICs could be as high as one kilowatt per square centimeter in an overall IC, and five kilowatts per square centimeter on smaller hot spots.

To that end, it has set up the Intrachip/Interchip Enhanced Cooling (ICECool) program and announced a $2.9m research funding grant to a team made up of the Georgia Institute of Technology and defense contractor Rockwell-Collins.

While DARPA’s (naturally undisclosed) needs for defense applications may exceed those for mainstream consumer and industrial markets, the differences in performance between military and civilian designs have been progressively narrowing. Its benchmarks are therefore pretty striking. The issue has also been known about but, to some extent, subordinated to challenges in reliably producing through-silicon-vias for 3D-ICs.

“There is really no good way to address this heat dissipation need with existing technology, and the problem is getting worse because computing power is increasing and the capabilities being put on chips are expanding,” said Yogendra Joshi, a professor in Georgia Tech’s Woodruff School of Mechanical Engineering and the project’s principal investigator.

3D-IC cooling challenges

In a statement, Joshi described the most pressing challenges facing the GeorgiaTech/Rockwell team. These are:

  • Implementing non-uniform cooling using liquid evaporation in 3D-ICs. The program calls for two dies to be cooled together, but the approaches developed for that could be used in multiple stacked dies. Being able to cool smaller areas with higher heat dissipation needs will provide an additional challenge.
  • Meeting reliability standards while ensuring that the coolant and vaporization within tiny microfluidic passages does not induce liquid dry-out, passage cracking, fluid leakage or undesirable electronic performance.
  • Fabricating micron-scale cooling structures smaller than the thickness of a hair in the integrated circuit stack and understanding the flow and heat transfer physics taking place at that scale.

The work will also extend into researching and modeling how liquids boil at the micron scale.

“The physics of how liquids boil has been well studied for large systems such as power plant boilers,” Joshi noted. “What we are talking about here is boiling that will take place in passages that are produced by microfabrication techniques that may be only 50 micrometers by 50 micrometers. The physics of what will be going on there is very different than what happens at the large scale, and how these liquids boil in the passages of interest will result in new scientific insights.”

Ultimately, the team hopes to identify a coolant that meets necessary phase change performance requirements without damaging the 3D-ICs.

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