“Variation is now unavoidable. The challenge is how you make your design more immune to it.” So says Zhihong Liu, executive chairman of ProPlus Design Solutions.
ProPlus has done well out of variation over the years. The company can trace its history back 20 years in the device modeling business, and it is one of the foundries’ leading partners in that sphere. But this month, it is taking a leap beyond its SPICE modeling business into full-blown simulation, targeting increasingly thorny design-for-yield (DFY) issues.
Its new NanoSpice parallel SPICE simulator joins the company’s existing BSIMProPlus modeling software and NanoYield variation analysis platform to provide what Liu now sees as a complete DFY front-end package.
“There are three DFY challenges. First, you have to capture the variation. Second, you have to analyze it. And third you have to predict its impact on your design. We already had the first two, so it made sense to move to the third. And it was something we thought we should do – today’s customers want turnkey solutions, not just point elements,” says Liu.
The DFY simulation challenge
Simulation has been proving progressively more challenging for all suppliers with each sub-nanometer process. As the industry progresses through ever smaller nodes, the ‘consistency’ previously seen in variation has got smaller and smaller. From lot to lot, from wafer to wafer, from die to die and from device to device, different issues crop up, so getting the immunity Liu talks about has become harder and harder.
“The most realistic way to approach this, as you see simulation times move out from hours to weeks, is to be able to apply an efficient, very fast multi-variance statistical analysis – Monte Carlo simulations,” says Liu.
“But Monte Carlo isn’t free. You need information within the simulator to get the greatest efficiency and the best results. That is where our expertise in device modeling and our partnerships with the foundries make the difference. We can insert that intelligence.”
It is also how ProPlus sees itself differentiating its simulation offering from those out of the leading vendors. “NanoSpice is integrated at the code and kernel level with our yield analysis,” says Liu. “Nobody else can offer that.”
NanoSpice simulation results
Certainly, the performance claims that accompany the NanoSpice launch are striking.
It simulated a multi-million element, post-layout analog/digital converter (ADC) circuit in less than two days with pure SPICE-comparable accuracy measured in signal-to-noise ratio (SNR). Typical parallel SPICE simulators can take several weeks to complete this task.
In another example, a 50-million transistor SRAM block was successfully simulated using NanoSpice in memory mode when other parallel SPICE simulators could not run a design this large.
In a recent evaluation, NanoSpice ran sign-off simulation on a 576-million element, full-chip memory circuit in eight hours using eight threads with 15 gigabytes of memory consumption.
If you want to know more, the company will host an online webinar going under NanoSpice’s hood on April 25th at 11am PDT.