DAC 2013 Preview II: Panels

By Paul Dempsey |  No Comments  |  Posted: April 8, 2013
Topics/Categories: Conferences, Design to Silicon, Digital/analog implementation, Blog - EDA, Embedded, - Tested Component to System, Verification  |  Tags: , , , , ,

Our second DAC 2013 preview article focuses on some of the panel sessions running both as part of the main conference and in the DAC Pavillion on the exhibition floor. We don’t have space to list all of them – these just caught our eye for a few of the reasons we outline below – and you probably want to check out the main DAC 2013 program because there is plenty of meat in there.

We’ve also assumed that Gary Smith’s DAC 2013 kick-off (Monday June 3rd, 9.15am, Pavillion) and Jim Hogan’s annual conflab (Tuesday June 4th, 10.15am, Pavilion) are already on many of your ‘to do’ lists.

One other quick piece of housekeeping. All Pavilion panels run for one hour, except the Kaufman interview, which is 45 minutes. All conference panels run for 90 minutes.

Monday June 3

Phil Kaufman Award Winner – Interview
11.15am, Exhibition Floor, DAC Pavilion

And this year’s recipient really is the man of the hour. Dr Chenming Hu led the UC-Berkeley team that has given us the finFET, thereby essentially setting the path for the industry beyond 20nm. With many companies looking to skip 20nm planar and go straight to these 3D structures (or that remarkably similar triGate thingamajig), DAC 2013 will inevitably be finFET-packed. Expect Dr Hu’s early conference thoughts to be agenda-setting in every sense.

Will a data explosion blow up the IC design flow?
3:15 PM, Exhibition Floor, DAC Pavilion

Tech Design Forum‘s own Chris Edwards wrangles experts including ARM’s Rob Aitken, Mentor Graphic’s Juan Rey and GlobalFoundries’ Christopher Spence as they aim to give DAC 2013 some tips on how to manage the massive volume of information needed to realize today’s SoC’s. We’re promised a wide-ranging debate stretching across methodology, data standards and design IT infrastructure.

Tuesday June 4

Organizational and management solutions to the verification crisis
1:30 PM, Exhibition Floor, DAC Pavilion

We stick with the industry’s struggle to master proliferation for our next panel. Have we reached the point where verification doesn’t just feel “endless” but has actually become “insuperable”? Our guess is we haven’t, but again we need strategies that at least give us a silicon Jenny Craig. Cadence’s Mike Stellfox will seek to draw practical advice at DAC 2013 from Intel’s Neeta Ganguly, ARM’s Alan Hunter and Qualcomm’s Scott Runner.

Is security the next design dimension?
4:00 PM, Conference, Room 16AB

Embedded system security has become a critical issue not just technologically, but also economically and politically. From cars and voting booths to power plants and hospitals, security concerns have become as pervasive as electronics itself. But how do you define security features and best integrate them alongside ‘traditional’ flow factors such as cost, power, and reliability. U-Mass’ Wayne Burleson will be joined at DAC 2013 to discuss your (and President Obama’s) headaches by experts from industry and academia. Panelists include Sateesh Adeppalli of Cisco Systems, Srini Devadas from MIT, Kevin Gotze from Intel and Patrick McDaniel from Penn State.

Wednesday June 5

Disruptive verification technologies: Can they really make a difference?
9:00 AM, Conference, Room 16AB

We make no apologies for highlighting the flipside of the verification debate due in this exploration of some new verification techniques that may in help address the current crisis beyond managing the tools we have more efficiently. Chances are we’ll need to do both. This DAC 2013 conference panel is moderated by consultant Brian Bailey and will feature Intel’s Ken Albin, Michigan-Ann Arbor’s Valeria Bertacco, ARM’s John Goodenough, Breker Verification Systems’ Adnan Hamid and Alan J. Hu from the University of British Columbia.

Test/Diagnose/Debug: Let the 3D-IC chaos begin
1:30 PM, Conference, Room 16AB

Well, at least the title’s honest on this one. Seriously though, interposer technology is here although the volume implementation of heterogeneous 3D stacking recently appeared to move out again (there will be a fair few DAC 2013 attendees looking for clarity there). These technologies will only get traction if the industry has greater confidence in related test, diagnosis and debug processes. Cisco’s Bill Eklow will look at how far we’ve got with Krishnendu Chakrabarty of Duke University, Al Crouch of ASSET InterTech, Mike Shapiro of IBM and Xilinx’s Shahin Toutounchi.

EDA meet analytics. Analytics meet EDA
4:00 PM, Conference, Room 16AB

Yup, verification again – but perhaps even more than that. Statistical analysis, data mining, machine learning, and more. We’ve already seen some of these techniques used in functional verification, but where else could they prove of value – and not just in verification but throughout the flow? Synopsys’ Janick Bergeron will extract the thoughts of Freescale Semiconductor’s Jay Bhadra, Mentor’s Harry Foster, UC-Santa Barbara’s Li-C Wang, IBM’s Avi Ziv and Fei Xei of Portland State.

Thursday June 6

Analog design with finFETs: “The Gods must be crazy!”
1:30 PM, Conference, Room 16AB

So, the digital guys have all jumped on finFETs with great enthusiasm. Not surprisingly, many of their analog counterparts are more phlegmatic – these guys like their existing schematics, thank you very much. So, how quickly will things change… or not? Altera’s Ron Wilson moderates as Cadence’s Anirudh Devgan, Freescale’s Scott Herrin, Synopsys’ Navraj Nandra and TSMC’s Eric Soenen warily eye the hornet’s nest.

Cyber-physical system software: Emperor’s new clothes or not?
3:30 PM, Conference, Room 16AB

We’re all suckers for a new term, particularly one that sounds like the cue for a new Terminator sequel. “Cyber-physical systems (CPS)” in truth reflects the broad system level trend to view cars, buildings and the smart grid in a more holistic way than implied by the traditional embedded view. It also provides important context for the move into the Internet of Things. So, what are the coding implications here? Peter Marwedel of Dortmund Technical University moderates a DAC 2013 panel made up of Lund University’s Karl-Erik Arzen, Marco Di Natale of Pisa’s Scuola Superiore Sant’Anna, Rolf Ernst of Braunschweig Technical Univesity, Rajesh Gupta of UC-San Diego and Freescale’s Rob Oshana.

Don’t forget to read our other 2013 preview articles:

DAC 2013 Preview I: Putting users first and marking 50 years

DAC 2013 Preview III: Embedded

DAC 2013 Preview IV: Management and Training Days

DAC 2013 Preview V: Rounding out the keynotes

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