The GSA Memory+ Conference takes place on Thursday October 31 at The Regent Hotel in Taipei, Taiwan and looks like an event well worth checking out for anyone looking at the challenges of 3D-IC. October 24 (Thursday) is also the last official day for online registration before the event.
While memory is the focus, another critical strand looks at “system integration/optimization between logic and memory”. We have already come some way with homogeneous memory stacking. But the work towards heterogenous stacking – logic on memory, typically – is less mature. Though help is on the way (as Steve Smith explains here), the more we can all get the better.
The GSA has recruited speakers from a strong group of companies, including Dr Ronald Black, president and CEO of Rambus. Toshiba, Samsung and Macronix also provide senior presenters.
From a general point of view, a couple of things caught our attention.
Packaging is too often one of the forgotten challenges for 3D-IC. A keynote has been scheduled that will discuss this at the source. Dr. Choon-Heung Lee, Corporate Technology Officer & Corporate Vice President of Amkor Technology, will outline “Where Is the Packaging World Headed?”
The conference’s afternoon sessions go directly into specific 3D-IC challenges across the design flow, with input from TSMC at the foundry level, Cadence Design Systems at the EDA level, and Advantest at the test level. Again, the speakers are all excellent, well-known figures in the business.
- Jerry Tzou, Deputy Director for the Backend Business Division at TSMC, will address “3D-IC Enablement”.
- Dr. Vassilios Gerousis, Distinguished Engineer & Technologist at Cadence, will provide an overview of “3D-IC Design Technology – Where are We?”
- C.H. Wu, President of Advantest Taiwan, will address “Stacked Memory Test Challenges”.
The conference is free to attend for GSA members and students. NT$3,000 ($105) for others. It runs from 9.00am-4.30pm.