Synopsys doubles speed of formal ECO checking

By Luke Collins |  No Comments  |  Posted: June 17, 2013
Topics/Categories: Design to Silicon, RTL, Verification  |  Tags: ,  | Organizations: ,

Synopsys’ Formality equivalence-checking tool has been extended to help designers implement functional ECOs more quickly and easily.

“Customers are telling us that designs go through three, six and sometimes more cycles of ECO per project, implementing multiple changes per cycle,” said Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group, in an introductory video. “This typically takes a few days per change, translating to four to 10 engineering weeks per project.”

Formality Ultra, an add-on to Formality, includes matching technologies that help designers implement ECOs, and a verification engine that can check that the changes introduced have not altered the design’s functionality. Synopsys says the tool can verify the correctness of an ECO in minutes for multimillion-instance designs. The two enhancements can halve the time it takes to implement and check functional ECOs, and should also make the process more predictable.

According to Domic, for the implementation phase, the tool matches and can visually highlight the equivalent nets in the modified RTL and the original netlist, so that designers can identify where the netlist changes should be made. For the checking phase, Formality Ultra can automatically identify the subset of the design that is affected by each ECO, then works out which cones of logic need to be verified. It can then verify just those logic cones, working on them concurrently, rather than having to reverify the whole design.

The tool also outputs a script for IC Compiler, the Synopsys place and route tool, which indicates the full path to all the cells affected by each ECO, so that the layout can be adapted using IC Compiler’s incremental place and route capabilities.

Because the ECO checks take minutes to run, rather than hours for a full verification, engineers have more scope to explore ‘what if?’ scenarios as they implement the ECOs. Some companies are already taking advantage of the new capabilities in new ways. In a statement, Bruce Fishbein, vice president of NCD IC Engineering at Cavium, said: “[Formaility Ultra] will enable us to implement more complex functional changes as ECOs rather than wait for the next derivative of the design.”

There’s a demo video on Formality Ultra here.

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