Toward more efficient formal strategies for deadlock
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
Blog Topics
Earlier latch-up prevention with topology-based analysis
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
Verific celebrates two decades of parser pre-eminence
The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.
MRAM pushes speed and endurance at IEDM
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Siemens and Arm combine to extend digital twin further into SoC design
Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
On-demand DRC within P&R cuts closure time in half for MaxLinear
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
Capacitive link to power cheap wireless tags
Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
Automating the pain out of clock domain crossing verification
A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm
Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.