Blog Topics

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.

Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.

SureCore has started running 30-day trials of its low-power memory compiler.

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.