Blog Topics

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Wind River has set up a site to distribute more experimental libraries based around its real-time operating systems and provide a hub for users to interact.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.